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5T995 - Block Diagram


2.5V Programmable Skew PLL Clock Driver

Alternative Products
NOTICE - The following device(s) are recommended alternatives:
Functionally compatible

The 5T995 is a high fanout 2.5V PLL based clock driver intended for high performance computing and datacommunications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T995 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The 5T995 has LVTTL outputs with 12mA balanced drive outputs.


  • Reference input is 3.3V tolerant
  • Four pairs of programmable skew outputs
  • Low skew: 185ps same pair, 250ps all outputs
  • Selectable positive or negative edge synchronization: Excellent for DSP applications
  • Synchronous output enable
  • Input frequency: Std: 2MHz to 160MHz
  • A: 2MHz to 200MHz
  • Output frequency: Std: 6MHz to 160MHz
  • A: 6MHz to 200MHz
  • Three-level inputs for skew and PLL range control
  • Three-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
  • PLL bypass for DC testing
  • External feedback, internal loop filter
  • 12mA balanced drive outputs
  • Low Jitter: <100ps cycle-to-cycle
  • Power-down mode
  • Lock indicator
  • Standard and A speed grades
  • 2.5V VDD
  • -40°C to 85°C ambient operating temperature
  • Available in TQFP package
  • Not Recommended for New Design

Product Specification

Additive Phase Jitter Typ RMS (ps)Output Skew (ps)Core Voltage (V)Inputs (#)Input TypeInput Freq (MHz)Output Voltage (V)Outputs (#)Output TypeOutput Freq Range (MHz)

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5T995APFIObsoletePP44TQFP44INoTrayCheck Availability
5T995APFI8ObsoletePP44TQFP44INoReelCheck Availability
5T995APPGIObsoletePPG44TQFP44IYesTrayCheck Availability
5T995APPGI8ObsoletePPG44TQFP44IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (11)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB Dec 22, 2013
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB Oct 27, 2013
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016