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5V9351 - Block Diagram


LVCMOS Clock Generator

The 5V9351 is a high performance, zero delay, low skew, phase-lock loop (PLL) clock driver. It has four banks of configurable outputs. The 5V9351 uses a differential PECL reference input and an external feedback input. These features allow the 5V9351 to be used as a zero delay, low skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK, a CMOS clock driver input. If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing so, the 5V9351 will be in clock buffer mode. Any clock applied to TCLK will be divided down to four output banks. When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will be clocked in both phase and frequency to FBIN. PECL clock is activated by setting REF_SEL to low.


  • Fully integrated PLL
  • Output frequency up to 200MHz
  • 2.5V and 3.3V Compatible
  • Compatible with PowerPC™, Intel, and high performance RISC
  • microprocessors
  • Output frequency configurable
  • Cycle-to-cycle jitter max. 22ps RMS
  • Compatible with MPC9351

Product Specification

Core Voltage (V)Input Freq (MHz)Inputs (#)Input TypeOutput Voltage (V)Output Freq Range (MHz)Output TypeOutputs (#)C-C Jitter Max P-P (ps)
2.5, 3.325.000000 - 200.0000002LVPECL, LVTTL2.5, 3.325.000000 - 200.000000LVTTL, LVCMOS9

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5V9351PFGIObsoletePRG32TQFP32IYesTrayCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 16, 2014
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB Dec 22, 2013
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB Oct 27, 2013
show all (8)
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 14, 2012
PCN# : A-0610-02 ASAT China as Alternate Facility for CABGA/CVBGA/FPBGA/TQFP/PQFP Product Change Notice PDF 252 KB Oct 19, 2006
A-0603-04 Transfer TQFP and PQFP from ASAT HK to ASAT China Product Change Notice PDF 164 KB May 10, 2006
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products Product Change Notice PDF 80 KB Dec 14, 2004
PCN#: A-0310-01, Green Products Product Change Notice PDF 26 KB Oct 10, 2003
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016