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672-01 - Block Diagram
672-01 - Pinout


Quadraclock Quadrature Delay Buffer

The 672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT's proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the 672-01 and up to 135 MHz for the 672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The 672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin. IDT manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world.


  • Packaged in 16-pin SOIC
  • Pb (lead) free package, RoHS compliant
  • Input clock range from 5 MHz to 150 MHz (depends multiplier)
  • Clock outputs from up to 84 MHz (672-01) and up 135 MHz (672-02)
  • Zero input-output delay
  • Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections
  • Four accurate (<250 ps) outputs with 0°, 90°, 180°, and 270° phase shift from ICLK, and one FBCLK (0°)
  • Separate supply for output clocks from 2.5 V to 5 V
  • Full CMOS outputs (TTL compatible)
  • Tri-state mode for board-level testing
  • Includes Power-down for power savings
  • Advanced, low power, sub-micron CMOS process
  • 3.3 V to 5 V operating voltage
  • Industrial temperature version available

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
4LVCMOS15.000000 - 84.0000005.000000 - 150.0000001LVCMOS13.3, 53.3, 5

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
672M-01LFObsoleteDCG16SOIC16CYesTubeCheck Availability
672M-01LFTObsoleteDCG16SOIC16CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
672-01 Datasheet Datasheet PDF 78 KB Jul 30, 2012
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (10)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 245 KB Sep 11, 2013
PDN# : U-13-05R2 PRODUCT DISCONTINUANCE NOTICE (REVISED) Product Discontinuation Notice PDF 161 KB Oct 29, 2013
PDN# : U-13-05R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 161 KB Jul 25, 2013
PDN# : U-13-05 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 159 KB Apr 10, 2013
show all (4)
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB Oct 6, 2006
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
672-01 3.3V IBIS Model Model - IBIS ZIP 3 KB Mar 10, 2006
672_3 Model - IBIS ZIP 3 KB Mar 10, 2006
672_5 Model - IBIS ZIP 3 KB Mar 10, 2006