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82V3155 - Block Diagram
82V3155 - Pinout


Enhanced T1/E1/OC3 WAN PLL With Dual Reference Inputs

Alternative Products
NOTICE - The following device(s) are recommended alternatives:

The 82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3155 provides 10 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o, C155) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3155 is compliant with AT&T TR62411, Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port, 155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1, and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The 82V3155 can be used in synchronization and timing control for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse source. It also can be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs, line cards and SONET/SDH equipments.


  • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application
  • Supports ITU-T G.813 Option 1 clocks
  • Supports ITU-T G.812 Type IV clocks
  • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
  • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
  • Accepts two independent reference inputs which may have same or different nominal frequencies applied to them
  • Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o, C32o and C155 output clock signals
  • Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,F32o, RSP and TSP
  • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1
  • Holdover frequency accuracy of 0.025 ppm
  • Phase slope of 5 ns per 125 ?s
  • Attenuates wander from 2.1 Hz
  • Fast lock mode
  • Provides Time Interval Error (TIE) correction
  • MTIE of 600 ns
  • JTAG boundary scan
  • Holdover status indication
  • Freerun status indication
  • Normal status indication
  • Lock status indication
  • Input reference quality indication
  • 3.3 V operation with 5 V tolerant I/O
  • Package available: 56-pin SSOP (Green option available)

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)App Jitter ComplianceProg. Clock
16, 17LVCMOS, LVTTL, LVDS0.008000 - 32.768000, 0.008000, 1.544000, 2.048000, 3.088000, 4.096000, 6.312000, 8.192000, 16.384000, 19.440000, 32.768000, 155.5200000.008000, 1.544000, 2.048000, 19.4400002LVTTL, LVCMOS173.3ETSI-ETS, TR62411, ITU-T G.812, Stratum 4, Stratum 4E, Telcordia, ITU, ITU-T G.813 (Option 1), ETS 300 011, GR-1244-CORENo

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
82V3155PVObsoletePV56SSOP56CNoTubeCheck Availability
82V3155PVGObsoletePVG56SSOP56CYesTubeCheck Availability
82V3155PVG8ObsoletePVG56SSOP56CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
82V3155 Data Sheet Datasheet PDF 513 KB May 6, 2015
82V3155 Data Sheet Change Notice Datasheet PDF 87 KB Nov 18, 2004
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 78 KB Apr 29, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (14)
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
AN-406: WAN PLLs, FAQs Application Note PDF 60 KB Jul 17, 2003
PDN# : CQ-15-03 Quarter PDN for Declined Market Product Discontinuation Notice PDF 542 KB May 5, 2015
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 14, 2012
PCN# A-0508-02: OSET Alternate Assembly Location for Green Product Change Notice PDF 18 KB Sep 2, 2005
show all (7)
PCN#A-0504-02R1: Assembly Transfer IDT-Manila to OSE-Ph Product Change Notice PDF 16 KB Jul 22, 2005
PCN#: TB-0504-01, Transfer Test & Backend from IDT-Manila to IDT Product Change Notice PDF 35 KB Apr 29, 2005
PCN#: A-0504-02, Transfer assembly facility IDT-Manila to OSE-Ph Product Change Notice PDF 47 KB Apr 29, 2005
PCN#: A-0405-06, To qualify alternate facility ATP for PV (SSOP) Product Change Notice PDF 22 KB May 24, 2004