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82V3389 - Block Diagram
82V3389 - Pinout


Synchronous Ethernet WAN PLL

The 82V3389 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, 4E, 4, EEC-Option 1, EEC-Option 2 and SMC clocks in SONET / SDH / Ethernet equipments, DWDM and Wireless base station, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.5 MHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial. In general, the device can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure. See Chapter 4 Typical Application for details.


  • Features 0.5 MHz to 560 Hz bandwidth
  • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet
  • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
  • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
  • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
  • Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
  • Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
  • Integrates T0 DPLL and T4 DPLL
  • T4 DPLL locks independently or locks to T0 DPLL
  • Supports Forced or Automatic operating mode switch controlled by an internal state machine
  • it supports Free-Run, Locked and Holdover modes
  • Supports programmable DPLL bandwidth (0.5 MHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps)
  • Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
  • Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
  • Supports phase absorption when phase changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
  • Supports programmable input-to-output phase offset adjustment
  • Limits the phase and frequency offset of the outputs
  • Supports manual and automatic selected input clock switch
  • Supports automatic hitless selected input clock switch on clock failure
  • Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
  • Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2 kHz and an 8 kHz frame sync output signals
  • Provides 5 input clocks whose frequency cover from 2 kHz to 622.08 MHz
  • Provides 5 output clocks whose frequency cover from 1 Hz to 622.08 MHz
  • Provides output clocks for BITS, GPS, 3G, GSM, etc.
  • Supports PECL/LVDS and CMOS input/output technologies
  • Supports master clock calibration
  • Supports Master/Slave application (two chips used together) to enable system protection against single chip failure
  • Supports frequency monitor hysteresis
  • Supports Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783
  • Multiple microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial
  • IEEE 1149.1 JTAG Boundary Scan
  • Single 3.3 V operation with 5 V tolerant CMOS I/Os
  • 100-pin TQFP package, Green package options available

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Phase Jitter Typ RMS (ps)App Jitter Compliance
7LVDS, LVCMOS, LVPECL0.000001 - 622.0800000.002000 - 622.0800006LVDS, LVCMOS, LVPECL73.31000.800GR-253-CORE, GR-1244-CORE, ITU-T G.812, ITU-T G.8262, ITU-T G.783, ITU-T G.813, SMC, Stratum 3, 4 Clocks, 4E

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
82V3389BEQGActiveEQG100TQFP100CYesTrayCheck Availability
82V3389BEQG8ActiveEQG100TQFP100CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 567 KB Aug 26, 2016
PCN# : A1402-02 Alternate Assembly Locations Product Change Notice PDF 34 KB Sep 28, 2014