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Low Skew, 1-to-5 HSTL Zero Delay Buffer

Alternative Products
NOTICE - The following device(s) are recommended alternatives:
Pin-to-pin compatible

The 8624 is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8624 has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.


  • Fully integrated PLL
  • Five differential HSTL output pairs
  • Selectable differential CLKx/nCLKx input pairs
  • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSLSSTL
  • Output frequency range: 31.25MHz to 700MHz
  • Input frequency range: 31.25MHz to 700MHz
  • VCO range: 250MHz to 700MHz
  • External feedback for “zero delay” clock regeneration
  • Cycle-to-cycle jitter: 25ps (maximum)
  • Output skew: 25ps (maximum)
  • Static phase offset: ±100ps
  • 3.3V core, 1.8V output operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • For replacement device use 8725BY-01LF

Product Specification

Core Voltage (V)Input Freq (MHz)Inputs (#)Input TypeOutput Voltage (V)Output Freq Range (MHz)Output TypeOutputs (#)C-C Jitter Max P-P (ps)
3.331.250000 - 700.0000002LVDS, HSTL, SSTL, HCSL, LVPECL1.831.250000 - 700.000000HSTL425

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8624BYLFObsoletePRG32TQFP32CYesTrayCheck Availability
8624BYLFTObsoletePRG32TQFP32CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PDN# : CQ-14-07 Quarter PDN for Market Declined Product Discontinuation Notice PDF 541 KB Nov 12, 2014
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 16, 2014
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB Mar 31, 2013
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
8624 IBIS Model - IBIS ZIP 41 KB Jan 4, 2010