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m1060 - Block Diagram
m1060 - Pinout



The M106X Series VCSO (Voltage Controlled SAW Oscillator) based clock PLLs are designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support FEC (Forward Error Correction) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.


  • Integrated SAW delay line
  • Output of 62.5 to 175 MHz
  • Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz)
  • Pin-selectable PLL divider ratios support FEC ratios
  • M1060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
  • M1061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
  • M1062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
  • LVPECL clock output
  • Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOSLVTTL
  • Loss of Lock (LOL) output pin
  • Narrow Bandwidth control input (NBW pin) to adjust loop bandwidth
  • Hitless Switching (HS) options with or without Phase Build-out (PBO) available to enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance during reference clock reselection
  • Single 3.3V power supply
  • Small 9 x 9 mm SMT (surface mount) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeCore Voltage (V)Phase Jitter Typ RMS (ps)
2LVPECL77.760000, 83.314300, 155.520000, 166.62860010.000000 - 700.0000002LVDS, LVPECL, LVCMOS3.30.250

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
M1060-11I155.5200ObsoleteCG36CLCC36IYesTubeCheck Availability
M1060-11I155.5200TObsoleteCG36CLCC36IYesReelCheck Availability
M1060-11I166.6286ObsoleteCG36CLCC36IYesTubeCheck Availability
M1060-11I166.6286TObsoleteCG36CLCC36IYesReelCheck Availability


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