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25-Bit Configurable Registered Buffer for DDR2

Alternative Products
NOTICE - The following device(s) are recommended alternatives:
Pin-to-pin compatible

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.


  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

Product Specification

Pkg. CodePkg. TypeLength (mm)Width (mm)Temp. Grade

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
SSTUAF32866CHLFObsoleteBFG96CABGA96CYesTrayCheck Availability
SSTUAF32866CHLFTObsoleteBFG96CABGA96CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
SSTUAF32866C Datasheet Datasheet PDF 615 KB Jun 19, 2008