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28-Bit Configurable Registered Buffer for DDR2

Alternative Products
NOTICE - The following device(s) are recommended alternatives:
Pin-to-pin compatible

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.


  • 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation
  • Inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS
  • Outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output

Product Specification

Pkg. CodePkg. TypeLength (mm)Width (mm)Temp. Grade

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
SSTUAF32868BHLFObsoleteBKG176CABGA176CYesTrayCheck Availability
SSTUAF32868BHLFTObsoleteBKG176CABGA176CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
SSTUAF32868B Datasheet Datasheet PDF 551 KB Sep 4, 2007