Skip to main content
Tsi721 - Block Diagram

TSI721

RapidIO Bridge

The Tsi721 converts from PCIe to RapidIO and vice versa and provides full line rate bridging at 20 Gbaud. Using the Tsi721 designers can develop heterogeneous systems that leverage the peer to peer networking performance of RapidIO while at the same time using multiprocessor clusters that may only be PCIe enabled. Using the Tsi721, applications that require large amounts of data transferred efficiently without processor involvement can be executed using the full line rate block DMA+Messaging engines of the Tsi721.

Features

  • x4 PCIe V2.1 to x4 S-RIO V2.1
  • Single port: x4, x2 or x1 support
  • 1.25, 2.5, 3.125 and 5 Gbaud support
  • Multiple DMA and Messaging channels/engines each capable of supporting full 20 Gbaud I/O
  • 8Kbyte packet buffering per DMA and Messaging Channel
  • 20 Baud line rate performance for 64 byte or larger packets, max TLP payload 256 bytes, max block DMA 64 Mbyte
  • PCI Express non-transparent bridging for transaction mapping
  • Lane reversal
  • Automatic Polarity inversion for PCI Express
  • Typical power 2W
  • Reach Support: 60 cm over 2 connectors
  • 100, 125, 156.25 MHz S-RIO and PCIe Endpoint compatible clocking options
  • JTAG 1149.1 and 1149.6
  • 13x13 mm FCBGA
  • Industrial and Commercial options

Product Specification

InterfaceThroughput (Gbps)Cut Through Latency (ns)Pkg. Type
PCIe16300FCBGA

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
TSI721A1-16GCLYActiveRM143FCBGA143CNoTrayCheck Availability
TSI721A1-16GILActiveHM143FCBGA143INoTrayCheck Availability
TSI721A1-16GILYActiveRM143FCBGA143INoTrayCheck Availability
TSI721A1-16GCLVActiveHMG143FCBGA143CYesTrayCheck Availability
TSI721A1-16GILHActiveHMH143FCBGA143INoTrayCheck Availability
TSI721A1-16GILVActiveHMG143FCBGA143IYesTrayCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
Tsi721 Datasheet Datasheet PDF 405 KB Apr 4, 2016
locked
Tsi721 Device Errata Errata PDF 102 KB Oct 2, 2012
User Guides & Manuals
no-lock
PCIe2 to S-RIO2 Bridging and Switching Evaluation Platform Quick Start Guide Guide PDF 130 KB Apr 20, 2015
no-lock
PCIe2 to S-RIO2 Bridging and Switching Evaluation Platform Manual Manual - Eval Board PDF 1.20 MB Apr 20, 2015
no-lock
Tsi721 User Manual Manual PDF 3.92 MB Jul 18, 2013
Other
no-lock
IDT PCI Express Solutions Overview 简体中文, 日本語 Overview PDF 945 KB Aug 4, 2016
no-lock
S-RIO Switch Feature Comparison Chart Product Brief PDF 50 KB Feb 16, 2016
no-lock
Supercomputing at the Mobile Edge Overview Overview PDF 939 KB Sep 25, 2015
show all (9)
no-lock
PCIe2 to S-RIO2 Bridging and Switching Evaluation Platform Schematic Schematic PDF 1.18 MB Apr 7, 2015
no-lock
S-RIO Linux Support Miscellaneous PDF 12 KB Mar 25, 2015
no-lock
Tsi721 Product Brief Product Brief PDF 941 KB Apr 19, 2012
no-lock
Tsi721 Header File Miscellaneous TXT 221 KB Jul 5, 2011
no-lock
RapidIO2 Switch Overview Portfolio Overview PDF 4.03 MB Mar 1, 2011
no-lock
Tsi721 Pinlist and Ballmap Pinlist-Ballmap ZIP 127 KB Oct 29, 2010

Software & Tools

Title Type Format File Size Datesort icon
no-lock
Tsi721 BSDL Model Model - BSDL TXT 22 KB Jun 17, 2011
no-lock
Tsi721 IBIS Model - 2.5V Model - IBIS TXT 290 KB Feb 22, 2012
no-lock
Tsi721 IBIS Model - 3.3V Model - IBIS TXT 298 KB Mar 16, 2015
no-lock
Tsi721 Thermal Compact Model (Flotherm) FCBGA 2R Model - Thermal ZIP 1 KB Mar 18, 2010
no-lock
Tsi721 Thermal Compact Model (Flotherm) FCBGA Detailed Model - Thermal ZIP 9 KB Mar 18, 2011
no-lock
Tsi721 RapidFET 3_2_003 Module Software Tool ZIP 419 KB Dec 20, 2012

Related Videos

  • 2013-11-20 Introduction to Serial RapidIO® (SRIO) by IDT
  • 2015-06-17 Supercomputing at the Edge with Serial...