Skip to main content

Freescale™ MSC8144AMC-S

Overview 

The Freescale™ MSC8144AMC-S provides an AMC debugging environment for engineers developing applications for the MSC8144 series of Freescale DSPs. The MSC8144AMC-S single-width AMC board is designed around four Freescale MSC8144 DSPs. 
 
             
 
Each MSC8144 has 256 MB of associated 32-bit-wide DDR2 memory. High throughput RapidIO links connect the four MSC8144s to each other and to the data backplane. The RapidIO interfaces can run in x1 or x4 mode and are interconnected via the IDT Tsi578. For the control plane, each MSC8144 RGMII gigabyte Ethernet port is linked to the backplane ports through an Ethernet switch. An optional shared TDM interface is routed from each MSC8144 to the backplane extended ports.
 
For bootstrap purposes, a common I2C bus and EEPROM are connected between the MSC8144 devices. The EEPROM is programmed through a master MSC8144 or an in-circuit programmer attached to a header. AMC board management is handled via a Module Management Controller based around a Freescale MCF5213. The provides the board with power sequencing, hot swap functionality, temperature sensing, and FRU record storage. A number of debug and programming headers are offloaded to an expansion card through the front panel.
 
AMC Block Diagram
 
             
 
The available design collateral can help accelerate customer and third parties in their development phases and greatly reduce designers’ time to market.
 
For more information about the Freescale MSBA8100ADS, see www.freescale.com
 
 
FEATURES 
  • Target use
    • System component for baseband, media gateway, and RNC systems 
    • Software development platform for baseband, media gateway, and RNC solutions 
    • Design reference and enablement platform for customers and third parties
  • Form factor. Single-width AMC size, full height module
  • Connectivity
    • Two RapidIO x4 interfaces from backplane ports 4–7 and 8–11 routed to DSP farm via a Tsi578 RapidIO switch
    • Two RapidIO x4 interfaces from backplane extended ports 12–15 and 17–20 routed to DSP farm via a Tsi578 RapidIO switch 
    • 1000 Base-X Gigabit Ethernet from backplane ports 0 and 1 routed to DSP farm via Ethernet switch
    • Gigabit Ethernet routed to front plane expansion connector via a switch
    • E1/T1 TDM connection consisting of 8x (TX + RX) and common clock and sync on an AMC connector 
    • Each MSC8144 UART interface is multiplexed via the CPLD to a single RS-232 connector on the expansion connector 
    •  I2C bus connecting MSC8144s for boot and configuration
  • Hardware blocks
    • Four MSC8144 DSPs (four cores per device), each with the following:  
      • x4 RapidIO interface routed to a Tsi578 RapidIO switch
      • RGMII interface routed to an Ethernet switch
      • TDM routed to a CPLD for multiplexing to the backplane 
      • I2C interface for boot 
      • 256 MB of 32-bit DDR2 memory
    • RapidIO switch
      • Four lanes of x4 RapidIO lines from the MSC8144 farm
      • RGMII interface routed to an Ethernet switch
      • TDM routed to a CPLD for multiplexing to the backplane 
    • Ethernet switch 
      • Four lanes of RGMII from the MSC8144 farm
      • Two lanes of 1000Base-X to ports 0 and 1 of the backplane
      • One lane of SGMII to the front panel expansion connector
          
    • TDM. MSC8144 TDM routed to backplanes ports 12–15 and 17–20
               (multiplexed with the RapidIO lines) 
    • UART. MSC8144 UARTs multiplexed to the expansion connector 
  • Boot. Boot mode defined by switch: 
    • RapidIO interface via the backplane 
    • From the on-board I2C
  • MSC8144 debug. Chained JTAG header for four MSC8144s 
  • Module Management Controller 
    • Hot swapping
    • FRU storage 
    • Status LEDs 
    • Temperature and voltage monitoring 
  • Power supply 
    • 12 V and 3.3 V IPMCV, provided from AMC edge connector or terminal connector
    • On-board voltage requirements are generated via DC-DC voltage regulators:
      • 3.3 V for I/O 
      • 1.0 V for the MSC8144 cores and PLLs 
      • 2.5 V for M3 memory
      • 1.25 V for MSC8144 M3 memories and the Tsi578 core
      • 1.8 V/0.9 V DDR2 memory
      • 1.2 V, 1.5 V, and 2.5 V for the Ethernet switches 
 
APPLICATIONS 
  • System component for baseband, media gateway, and RNC systems 
  • Software development platform for baseband, media gateway, and RNC solutions 
  • Design reference and enablement platform for customers and third parties