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IDT PCIe2 to S-RIO2 (Tsi721-16GEBI) Evaluation Board


The IDT Tsi721-16GEBI  Evaluation Board is a prototyping platform that leverage’s IDT’s Tsi721 PCIe®  to RapidIO® Gen2 bridge as well as the CPS-1432 RapidIO Gen2 switch, allowing any PCIe processor to communicate to an S-RIO network. The Tsi721-16GEBI Evaluation board has a variety of interfaces that allows customers to interface DSPs, Microprocessors, and FPGAs to IDT switches, and also allows for x86 processors to interface to an S- RIO network through the Tsi721 bridge. Interfaces include AMCs, SMAs, InfiniBand/CX4 and SFP+ connectors. This allows customers to implement most network configurations that represent their production hardware in a logically equivalent manner. By doing so, systems firmware and software engineers can start implementing their code before production hardware is available thereby accelerating development cycles and time to market. 
The Tsi721-16GEBI evaluation board can network together multiple processors in individual PCs. Each PC is populated with a Tsi721 evaluation board. Each evaluation board is networked together over S-RIO, allowing for a cluster of PCIe enabled x86 processors over S-RIO.
The Tsi721-16GEBI evaluation board comes equipped with RapidFET JTAG, a software tool that can configure IDT switches and bridges out of band via the JTAG interface on the board, making access to registers simple via a user friendly Graphical User Interface. 
  • PCIe to S-RIO bridging
    • Tsi721 PCIe2 to S-RIO2 bridge with link speeds up to 5 Gbaud
  • S-RIO Switching Fabric 
    • Device: IDT CPS-1432   
    • Link speed: 6.25, 5, 3.125, 2.5, 1.25 Gbaud 
    • Protocol: S-RIO Gen1 (v1.3) or S-RIO Gen2 (v2.1) 
  • Industry-standard system interconnect connectors 
    • One PCIe x4 connector
    • One AMC B+ connector: x4 S-RIO links, Ports 4–7, 8–11, and 17-20 (No support for IPMC and JTAG)
    • Two SFP+ connectors: x1 S-RIO links
    • Two InfiniBand/CX4 connectors: x4 S-RIO links
    • One SMA array (x4 S-RIO link)
  • JTAG and  I2C 
    • JTAG header: 0.1” 10-pin headers
    • I2C header: 0.1” 10-pin header 
    • One I2C EEPROM per S-RIO device 
    • On-board USB to JTAG/I2C converter (FTDI FT2232HL)
  • Implement logical equivalent of production hardware configurations 
  • Reduce time to market by accelerating software and firmware design 
  • Learn about IDT Gen2 switches and bridges and pass packets between PCIe and RapidIO networks, allowing for the aggregation of x86 processors over RapidIO
  • Connect endpoint boards and evaluation platforms - with AMC, SMA, InfiniBand/CX4 and SFP+ connectors 
  • Backward compatible with RapidIO Gen1 AMCs and development platforms 
  • Easily configure with RapidFET JTAG - Standard (3-day trial of “Enhanced” functionality)
  • Conduct interoperability/interworking tests
  • Develop server and high performance computing systems with low latency, lower power RapidIO networks
  • Defense and Aerospace: Radar, sonar and navigations systems  
  • Medical Imaging:  CT Scanners, MRIs, Ultrasound   
  • Video:  Teleconferencing and Head End 
  • Wireless:  4G Baseband processing cards 
  • Server and High Performance Computing