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28-Bit 1:2 Registered Buffer with Parity

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.


  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Product Specification

Pkg. CodePkg. TypeLength (mm)Width (mm)Temp. Grade
BKG160, BK160CABGA139C

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
74SSTUBF32865ABKObsoleteBK160CABGA160CNoTrayCheck Availability
74SSTUBF32865ABK8ObsoleteBK160CABGA160CNoReelCheck Availability
74SSTUBF32865ABKGActiveBKG160CABGA160CYesTrayCheck Availability
74SSTUBF32865ABKG8ActiveBKG160CABGA160CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
74SSTUBF32865A Datasheet Datasheet PDF 383 KB Jun 19, 2008
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly Product Change Notice PDF 31 KB May 2, 2016

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