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74SSTUBF32866B

25-Bit Configurable Registered Buffer for DDR2

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

Product Specification

Pkg. CodePkg. TypeLength (mm)Width (mm)Temp. Grade
BFG96CABGA13.55.5C

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
74SSTUBF32866BBFGActiveBFG96CABGA96CYesTrayCheck Availability
74SSTUBF32866BBFG8ActiveBFG96CABGA96CYesReelCheck Availability

Documents

Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
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74SSTUBF32866B Datasheet Datasheet PDF 626 KB Dec 1, 2008
PCNs & PDNs
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PCN# : A1609-02 Alternate Site at OSET Taiwan on Select Packages Product Change Notice PDF 30 KB Oct 11, 2016
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PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB Oct 21, 2013

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