25-Bit Configurable Registered Buffer for DDR2

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
74SSTUBF32866BBFG Active BFG96 CABGA 96 C Yes Tray Availability
74SSTUBF32866BBFG8 Active BFG96 CABGA 96 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
74SSTUBF32866B Datasheet - Datasheet PDF 626 KB Nov 30, 2008
PCNs & PDNs
PCN# : A1609-02 Alternate Site at OSET Taiwan on Select Packages - Product Change Notice PDF 30 KB Oct 10, 2016
PCN#: A1309-03 Additional Assembly Sources - Product Change Notice PDF 398 KB Oct 20, 2013