3.3V 128K x 8 Asynchronous Static RAM Center Power & Ground Pinout
The 71V124 3.3V CMOS SRAM
is organized as 128K x 8. The JEDEC
pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL
-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
- JEDEC revolutionary pinout (center power/GND) for reduced noise
- Equal access and cycle times – Commercial: 10/12/15/20ns – Industrial: 10/12/15/20ns
- One Chip Select plus one Output Enable pin
- Inputs and outputs are LVTTL-compatible
- Single 3.3V supply
- Low power consumption via chip deselect
- Available in 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages.
|Density (Kb)||Bus Width (bits)||Core Voltage (V)||Pkg. Code||Organization||I/O Voltage (V)||Access Time (ns)||I/O Frequency (MHz)||Temp. Range||Architecture||Output Type |
|1024||8||3.3||PHG32, PBG32, PJG32||128K x 8||3.30||10, 12, 15||-40 to 85°C, 0 to 70°C||Asynchronous|| |