Synchronous Burst
The burst mode feature offers the highest level of performance to the system designer. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge.
Download the Packaging and Ordering SRAM Information (PDF) here.
Parametric Search
| Part Number | Density (Kb) | Bus Width (bits) | Core Voltage (V) | Pkg. Code | Organization | I/O Voltage (V) | I/O Frequency (MHz) | Temp. Range | Architecture | Output Type |
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