The 71V67803 3.3V CMOS SRAM is organized as 512K x 18. The 71V67803 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
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3.3V 512K x 18 Synchronous 3.3V I/O PipeLined SRAM
Software & Tools
|Title||Other Languages||Type||Format||File Size||Date|
|71v67803z_PF IBIS Model||-||Model - IBIS||ZIP||13 KB||Aug 13, 2000|