Question / Topic

What is the recommended Phase Detector input frequency setting in the 8V19N407 / 8V19N408?

Answer / Content

For low phase noise outputs, the phase detector frequency of both PLLs should be as high as possible but below 200 MHz. Other optimization criteria include the desired PLL bandwidth and loop filter component selection. Lower phase detector frequencies (1st stage PLL) support lower loop bandwidth values and smaller loop filter components and value.

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Documents

Title Other Languages Type Format File Size Date
Datasheets & Errata
8V19N407 Data Sheet - Datasheet PDF 759 KB Sep 30, 2015
8V19N408 Data Sheet - Datasheet PDF 735 KB Sep 30, 2015