How to Properly Terminate a Clock Signal by Identifying Common Signal Integrity Issues
This video describes how to analyze and properly terminate a clocking waveform. A good clock waveform is properly terminated when the output impedance of the driver and series resistance exactly matches the impedance of the transmission line. When the series resistance is too low for the transmission line, the waveform will exhibit overshoot, undershoot, and ringing. When the series resistance is too high, the waveform will exhibit a step on the rising and falling edges. By identifying the waveform characteristics, and then adjusting the series resistor up or down accordingly, you can often alleviate the most common termination-related issues in your circuit.
Presented by Ron Wade, clock expert at IDT.
For more information about IDT’s leading portfolio of clock buffer products, visit http://www.idt.com/products/clocks-timing/clock-distribution.