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PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview


• This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.


Hi, there. This is Ron Wade with IDT, and we’re going to talk about separate reference independence spread today, which is the latest PCI express clocking architecture. So let’s jump right in and define it and see what the implications are. So we have the CPU block here and we have our IO storage block here, and in this case they’re both being clocked by a spreading clock source, two separate spreading clock sources, and we have the PCI link between them. So the whole idea of doing this is to keep from having to send the clock over this, let’s say it’s a cable, keep it from sending a clock over the cable like you have to do today.

So one of the implications of this, one is you don’t have to send the clock over the cable when you have an SRIS system, but there’s some other things to take into account, too. The first is the minimum PPM on this spreading clock is minus 5300 for the PCI, say. The maximum is plus 300 PPM. In this situation, this clock could be at minus 53. This could be at 300, but that means is that this link here has to…the controllers have to, number one, know they’re in SRIS mode, and then insert what’s called the skip ordered set or dummy data into the link. When you do that, you’re going to lose from 1 to 3% of your performance. And the second issue here is there’s no mechanism today for the ends of the link to know that they need to be in SRIS mode to insert those skip ordered sets. So there’s no mechanism to say, “Hey, SRIS mode, please.”

So the second item or the next item is that besides the difference in jitter performance between the transmitter and the receiver and the difference between the jitter of the clock over here and the clock over here, now we have two separate spreads to take into account, and I’ve drawn the frequency harmonics, the 32 kilohertz of harmonics here. So these have to be taken into account so there’s a difference of the spreads also has to be noted. So it’s much more stringent to have a clock that meets this requirement than the other architectures already discussed.

So the specifications, they’re not final from the PCI-SIG on what a clock has to do to meet these requirements. Based on early indicators, we believe that we have clocks that are SRIS compatible today, and we can talk with you much more about that on one-on-one. So that’s a high level overview of SRIS, a couple of system architectures you usually have to look out for, and if you have any questions, you can email me at Thanks.