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What is Phase Jitter? A Brief Tutorial by IDT



A brief tutorial on phase jitter by IDT. Jitter terminology can be confusing and this video attempts to explain phase jitter in a concise format. The correct terminology is RMS phase jitter which is derived by integrating the area under the curve of a specific phase noise plot, at a specific carrier frequency, with a defined frequency range & offset. Presented by Sam Staker, Field Applications Engineer at IDT. Learn more about IDT’s leading timing solutions at



Hello. Welcome to ‘Time Out’ from IDT; the Number 1 world leader in timing solutions. My name is Sam Staker, and I’m a field applications engineer for IDT. Today we’re going to talk about an important question: What is phase jitter?
Before we do that, let’s talk a little bit about the terminology involved. Jitter can be very confusing. There are a lot of terms, engineers use them in different ways depending upon different applications: Phase jitter, phase noise and others. Before we get into phase jitter and phase noise, let’s take a step back and talk about jitter. 
The easiest place to understand jitter and the easiest place to start off is the time domain. We’ll look at an ideal clock signal versus a real-world clock signal. The picture on the top is an ideal clock. The signal period T is constant; the clock frequency, which is the reciprocal of time, is also constant. The rise and fall time is constant, it does not change. Obviously, this waveform is only seen in textbooks. On the bottom is a picture of a real world clock signal; the signal period varies, the frequency changes, the rise and fall time varies. This is the kind of clock signal that engineers see on oscilloscopes in their systems today. Jitter, very simply, is the deviation in time from the ideal reference clock. The picture on the top has no jitter; the picture on the bottom has jitter.
If you remember from engineering and math, if you do a fourier transform, you can take a signal and move it from the time domain to the frequency domain. If you do a fourier transform on that top signal, which is the signal without jitter, you’ll get a nice-looking pulse that’s represented here. That pulse is of amplitude A, which corresponds to the amplitude of a clock signal, but instead of a clock signal that goes up and down, you’ll get a pulse that is at the location of that clock frequency. Really what you get in the real world, though, is what’s on the bottom. If you do a fourier transform on a real-world clock, you’ll get something that looks like the picture on the bottom right. Obviously, most of the energy will be at that main frequency that’s represented by the peak, but instead of dropping off dramatically after that, it’ll drop off to the left and to the right. Those drop-offs, those ramps, are really defined by the error in that signal; the fluctuations in amplitude, the fluctuations in phase. Phase noise is the unintentional phase modulation on that specific carrier frequency. It’s the noise on the clock. The easiest way to think about it, it’s jitter, but its jitter in the frequency domain instead of time domain.
If we look at this frequency domain jitter, we’ll map it out in what we call a phase noise plot, and that is represented here. This is a specific example of a 100MHz carrier frequency or a 100MHz operating frequency, which is the peak that’s centered there in the middle of this graph. On specific applications, engineers may or may not care about this entire graph. In high-speed data coms, which is really a huge growing segment for these devices, they’re only going to look at a very small portion of that graph. That’s represented by that gray box down on the right. That frequency, that box, that range, is offset from that 100MHz carrier. That’s a frequency offset range, a frequency offset mask, or we’ll also call it a jitter mask. We’ll zoom in on that here in the next slide.
Zooming in on that very specific portion of the phase noise plot, here’s an example of a frequency window that’s 12kHz to 20MHz offset from that 100MHz operating or carrier frequency. If you take this curve and you integrate the area under that curve of a frequency range from f1 to f2 of 100.012MHz up to f2 of 120MHz; the number that comes out of that integration is what we call the RMS phase jitter. We care about these specific windows of jitter because that’s what’s driving these high-speed communication systems. Whether you’re SONET, gigabit Ethernet, or PCI express, you’ll have a specific offset, you’ll have a specific jitter mask; a specific window of noise that you care about. You’ll take that range, you’ll integrate it, and the number that comes out of that is the RMS phase jitter.
You can do the math that’s shown on the previous slide or you can take the easy way out. Luckily, we have electronic equipment that will make these measurements for us fairly easily. What you see on the slide there is a picture of a spectrum analyzer. We’ve taken the spectrum analyzer, we’ve hooked it up to a clock source that’s 155.52MHz, and we’ve zoomed in on a window 12kHz to 20MHz to the right of that peak frequency. The equipment will do the integration for us, which you can see on that picture. The numbers that you can see there are 245 femtoseconds of RMS phase jitter, and again, that phase jitter is 12kHz to 20MHz offset from the 155.52 carrier. 245 femtoseconds is world-class jitter performance, and this is done through our latest UFT, universal frequency translator 3rd generation clock generation device; industry-leading performance driving, high-speed data communications.
Now let’s answer our question of ‘What is phase jitter?’ It’s a little bit complicated, but as you can see, it’s not too involved coming up with the answer. Phase jitter, when people ask that they’re asking, ‘What is your RMS phase jitter?’ To come up with RMS phase jitter, we need to know what that carrier frequency is, what that operating frequency is, and we also need to have a well-defined offset range, or jitter mask, so we can integrate the area under that curve in the phase noise plot and come up with the number that’s specific to the engineer’s application. 
Also in summary, why should we care? Low RMS phase jitter equals low bit error rates. This is critical for today’s high-speed serial communications like 10Gig, 40Gig, 100-gigabit Ethernet, PCI Gen-3, and others. For the latest in industry-leading ultra-low phase jitter clocks, please visit Thanks for viewing today’s video and thanks for considering IDT clock devices.