DDR Zero Delay Clock Buffer

Features

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 266MHz (DDR 533)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
93732AFLF Obsolete PYG28 SSOP 28 C Yes Tube
Availability
93732AFLFT Obsolete PYG28 SSOP 28 C Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
93732 Datasheet Datasheet PDF 205 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1305-01 Gold Wire to Copper Wire Product Change Notice PDF 148 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
PDN# : K-08-09 PRODUCT DISCONTINUANCE NOTICE Product Delete Notice PDF 47 KB
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Boards & Kits