The 8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution Chip. The 8516 CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the 8516 provides a low power, low noise, pointto- point solution for distributing clock signals over controlled impedances of 100?. Dual output enable inputs allow the 8516 to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the 8516 ideal for those applications demanding well defined performance and repeatability.

Features

  • Sixteen differential LVDS outputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 700MHz
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input
  • Multiple output enable inputs for disabling unused outputs in reduced fanout applications
  • LVDS compatible
  • Output skew: 90ps (maximum)
  • Part-to-part skew: 500ps (maximum)
  • Propagation delay: 2.4ns (maximum)
  • Additive phase jitter, RMS: 148fs (typical)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free RoHS compliant package

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
8516FYLF Active TQFP 48 C Yes Tray Package Info
Availability
8516FYLFT Active TQFP 48 C Yes Reel Package Info
Availability

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
データシート
8516 Datasheet Datasheet PDF 334 KB
8516 IBIS Model Datasheet IBS 197 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PCN# : A1807-01 Gold wire to Copper Wire Product Change Notice PDF 32 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB