Use the following example for the calculations:
Jitter Attenuator Example
• Input CLK0 frequency: 25MHz
• Output Frequency: 125MHz (integer output divider)
• Output 2 Frequency: 155.52MHz (fractional output divider)
• Crystal frequency: 38.88MHz
• Crystal Doubler: Enabled
The device has an input pre-divider (P) that scales the input clock signal going into the digital PFD (phase frequency detector). It also has a feedback divider ratio (M1) that scales the feedback clock signal going into the same PFD. Ideally, both inputs into the PFD should have the same frequency. That relationship is expressed as follows:
Fpfd =Fin/P = Fvco/M1
Fpfd= phase frequency detector input frequency
Fin= input frequency
M1= lower loop feedback divider
P= input clock predivider
Fvco= VCO frequency
P and M1 must both be integers, so the relationship between P and M1 is the following:
M1= P*Fvco/Fin, rounded to the nearest integer
For each P value, a corresponding M1 value can be determined while the valid ranges for P and M1 are taken into consideration. The maximum PFD input frequency is 128kHz, or 0.128MHz. The recommended minimum PFD input frequency is 500Hz. From this, the minimum and maximum P values can be calculated as follows:
Pmin= Fin/PFDmax, (if this result is <1, then set Pmin=1)
Pmax= Fin/PFDmin (if this result is >2^20, then set Pmax=2^20)
M1 must then be calculated for the range, starting with Pmin in order to target the lowest input divider, ie, highest PFD input frequency for best performance.
Pmin<P <Pmax
When iterating through the P values, each P/M1 ratio should be compared to the ratio Fin/Fvco. Choose the first result that provides an error of 0. If such result is not found, then choose the result with the lowest error and a PFD frequency of >500Hz and <128KHz.
Refer to application note AN-860 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.


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AN-860 8T49N28X Frequency Programming Guide Application Note PDF 301 KB