The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures.
 
For information regarding evaluation boards and material, please contact your local IDT sales representative.
 

Features

  • PCIe Gen1–5 CC-compliant
  • Supports PCIe SRIS and SRNS clocking
  • Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
  • Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
  • SMBus-selectable CC/SRIS -0.25% spread
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
  • Easy AC-coupling to other logic families, see IDT application note AN-891.
  • Space saving 5 × 5 mm 40-VFQFPN

Product Options

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type 封装 Buy Sample
9FGL0641CKILF Active VFQFPN 40 I 100 Tray Package Info
Availability
9FGL0641CKILFT Active VFQFPN 40 I 100 Reel Package Info
Availability
9FGL0651CKILF Active VFQFPN 40 I 85 Tray Package Info
Availability
9FGL0651CKILFT Active VFQFPN 40 I 85 Reel Package Info
Availability

Documentation & Downloads

文档标题 他の言語 Type 文档格式 文件大小
数据手册与勘误表
9FGL02-04-06-08 Family Datasheet Datasheet PDF 580 KB
使用指南与说明
Timing Products for NXP (Freescale) i.MX ( 简体中文) English Guide PDF 321 KB
Timing Products for NXP (Freescale) i.MX ( 简体中文) English Guide PDF 321 KB
9FGx08 PCIe Clock Generator Evaluation Boards User Guide Manual - Eval Board PDF 838 KB
应用指南 &白皮书
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PCN# : A2005-01(R1) Add UTL, Thailand and JCET, China as Alternate Assembly Locations Product Change Notice PDF 725 KB
PCN# : A2005-01 Add UTL, Thailand and JCET, China as Alternate Assembly Locations Product Change Notice PDF 116 KB
PCN# : TP1910-02 Metal Change to Enhance Spread Performance Product Change Notice PDF 127 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : MM1610-01 Improve performance to meet the new PCIe Product Change Notice PDF 23 KB
Downloads
Software for PCIe Evaluation Kits Software ZIP 440 KB
9FGL06P1 IBIS Model Model - IBIS ZIP 203 KB
9FGL0651 IBIS Model Model - IBIS ZIP 89 KB
9FGL0641 IBIS Model Model - IBIS ZIP 89 KB
其它
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
9FGL06 Evaluation Board Schematic Schematic PDF 33 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB