The 8SLVD2102I is a high-performance differential dual 1:2 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2102I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2102I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with two low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Two 1:2, low skew, low additive jitter LVDS fanout buffers
  • Two differential clock inputs
  • Differential pairs can accept the following differential input
    levels: LVDS and LVPECL
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 15ps (maximum)
  • Propagation delay: 300ps (maximum)
  • Low additive phase jitter: 200fs, RMS (maximum);
    fREF = 156.25MHz, VPP = 1V, VCMR = 1V,
    Integration Range 10kHz - 20MHz
  • 2.5V supply voltage
  • Maximum device current consumption (IDD): 90mA
  • Lead-free (RoHS 6) 16-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
8SLVD2102NLGI Active VFQFPN 16 I Yes Tube Package Info
Availability
8SLVD2102NLGI/W Active VFQFPN 16 I Yes Reel Package Info
Availability
8SLVD2102NLGI8 Active VFQFPN 16 I Yes Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8SLVD2102 Datasheet Datasheet PDF 537 KB
Application Notes & White Papers
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Other
RF Timing Family Product Overview Overview PDF 464 KB
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IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB