The 85357I-01 is a 4:1 or 2:1 Differential-to-3.3V LVPECL / ECL clock multiplexer which can operate up to 750MHz. The 85357I-01 has 4 selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The device can operate using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or 3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects CLK0, nCLK0).


  • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer
  • One differential 3.3V LVPECL output
  • Four selectable CLK, nCLK inputs
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 750MHz
  • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input
  • Part-to-part skew: 415ps (maximum)
  • Propagation delay: 1.5ns (maximum)
  • LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.135V to -3.465V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
85357AGI-01LF Obsolete TSSOP 20 I Yes Tube Package Info
85357AGI-01LFT Obsolete TSSOP 20 I Yes Reel Package Info

Documentation & Downloads

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PDN# : CQ-15-01 (R1) Quarter PDN for Declined Market Product Discontinuation Notice PDF 550 KB
PDN# : CQ-15-01 Quarter PDN for Declined Market Product Discontinuation Notice PDF 547 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
85357I-01 IBIS Model Model - IBIS ZIP 24 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB