The 8A34001 System Synchronizer for IEEE 1588 generates ultra-low jitter; precision timing signals based on the IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE).  The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Digitally Controlled Oscillators (DCOs) are available to be controlled by IEEE 1588 clock recovery servo software running on an external processor. The device supports physical layer timing with Digital PLLs (DPLLs) and other timing blocks necessary to implement a Synchronous Equipment Timing Source (SETS) for SyncE. The DCOs can be controlled using IEEE 1588 information alone, or they can combine IEEE 1588 time information with physical layer frequency information from SyncE in accordance with ITU-T G.8273.2. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 Time Stamp Units (TSUs) in a system. The device supports multiple independent channels that control: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.


  • Eight independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 0.5Hz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • DCOs can be controlled by external IEEE 1588 software to synthesize Precision Time Protocol (PTP) / IEEE 1588 clocks with frequency resolution less than 1.11x10-16
    • Combo Bus simplifies compliance with ITU-T G.8273.2
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI


下单器件 ID Part Status Temp. Range Carrier Type Buy Sample
Active -40 to 85°C Reel
Active -40 to 85°C Tray


文档标题 其他语言 类型 文档格式 文件大小 日期
8A34001 Datasheet 数据手册 PDF 1.99 MB
8A3xxxx Firmware Version v4.8.7 Errata Notice 勘误表 PDF 44 KB
8A3xxxx Family Errata (Rev B with Update v4.7) 勘误表 PDF 127 KB
8A3xxxx Family Programming Guide (v4.8.7) 指南 PDF 2.33 MB
8A3xxxx Firmware Version 4.8.7 Release Notes 指南 PDF 101 KB
8A3xxxx Family Programming Guide (v4.8) 指南 PDF 3.60 MB
8A34xxx 144BGA EVK User Manual 手册 - 评估板 PDF 2.67 MB
ClockMatrix GUI Step-by-Step User Guide 指南 PDF 4.98 MB
应用指南 &白皮书
AN-807 Recommended Crystal Oscillators for Network Synchronization 应用文档 PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter 应用文档 PDF 1.57 MB
Using a Frame or Sync Pulse Input for Clock Alignment 应用文档 PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 应用文档 PDF 390 KB
Auto-Alignment of Outputs 应用文档 PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback 应用文档 PDF 155 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 应用文档 PDF 739 KB
AN-1033 Delay Variation Measurement and Compensation 应用文档 PDF 633 KB
AN-1034 Minimizing Backplane Signal Usage 应用文档 PDF 566 KB
AN-1031 Time Alignment Background in Wireless Infrastructure 应用文档 PDF 479 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System 应用文档 PDF 442 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment 应用文档 PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy 应用文档 PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment 应用文档 PDF 324 KB
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 产品变更通告 PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue 产品变更通告 PDF 123 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products 产品变更通告 PDF 435 KB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.1, FWv4.8.7) 软件 ZIP 46.93 MB
ClockMatrix Register Header Files v4.8.7 软件 ZIP 278 KB
8A340xx ClockMatrix IBIS Model 模型 - IBIS ZIP 2.40 MB
Timing Commander Installer (v1.16.2) 软件 ZIP 18.44 MB
8A34001P BSDL Model 模型 - BSDL ZIP 3 KB
8A34001 BSDL Model 模型 - BSDL ZIP 3 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 软件 ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 软件 ZIP 177 KB
8A340x1 BSDL Model 模型 - BSDL BSDL 15 KB
ClockMatrix BGA-144 Delphi Thermal Model with 1W Power 模型 - 热量 PDML 3 KB
ClockMatrix BGA-144 2-Resistor Thermal Model with 1W Power 模型 - 热量 PDML 2 KB
8A3x0xx Schematic Checklist (v1.22) 其它参数 XLSX 328 KB
ClockMatrix Family Overview 概览 PDF 241 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
ClockMatrix 144-BGA Devices Evaluation Board Schematic v1.1 原理图 PDF 288 KB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB