The 8V19N492 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.

A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.

The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The 8V19N492 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

特性

  • High-performance clock RF-PLL with support for JESD204B
  • Optimized for low phase noise: -150dBc/Hz (800kHz offset; 245.76MHz clock)
  • Integrated phase noise of 63fs RMS typical (12k–20MHz).
  • Dual-PLL architecture
  • 1st-PLL stage with external VCXO for clock jitter attenuation
  • 2nd-PLL with internal FemtoClockNG PLL: 2949.12MHz
  • Five output channels with a total of 15 outputs
  • Configurable integer clock frequency dividers
  • Supported clock output frequencies include: 2949.12, 1474.56, 983.04, 491.52, 245.76, and 122.88 MHz
  • Low-power LVPECL/LVDS outputs support configurable signal amplitude
  • Phase delay circuits
  • Redundant input clock architecture with two inputs and
  • SYSREF generation modes include internal and external trigger mode for JESD204B
  • Supply voltage: 3.3V
  • Package: 10 × 10 mm, 88-VFQFPN
  • Temperature range: -40°C to +105°C (Case)

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 88 I 是的 Tray
Availability
Active VFQFPN 88 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8V19N492 Datasheet 数据手册 PDF 1.72 MB
8V19N492 Short-Form Datasheet 简易格式数据手册 PDF 229 KB
使用指南与说明
8V19N49x Hardware Design Guide 指南 PDF 1.30 MB
应用指南 &白皮书
AN-952 8V19N480_490 Design Guide for JESD204B Output Phase Alignment and Termination 应用文档 PDF 975 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
Downloads
Timing Commander Personality File for 8V19N49x Devices (v5.0.1) 软件 ZIP 4.36 MB
其他
RF Timing Family Product Overview 概览 PDF 464 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
8V19N49x RF Sampling Clocks with Jitter Attenuation Overview 概览 PDF 1.21 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
RF-Grade Clock Jitter Attenuator and Frequency Synthesizer Product Brief 产品简述 PDF 847 KB