9ERS3165 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel processors and Intel based systems. 9ERS3165 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.

Features

  • 2 - CPU differential low power push-pull pairs
  • 9 - SRC differential low power push-pull pairs
  • 1 - CPU/SRC selectable differential low power push-pull pair
  • 1 - SRC/DOT selectable differential low power push-pull
  • 5 - PCI, 33MHz
  • 1 - PCI_F, 33MHz free running
  • 1 - USB, 48MHz
  • 1 - REF, 14.318MHz
  • CPU outputs cycle-cycle jitter < 85ps
  • SRC output cycle-cycle jitter < 125ps
  • PCI outputs cycle-cycle jitter < 250ps
  • +/- 100ppm frequency accuracy on CPU & SRC clocks
  • Does not require external pass transistor for voltage regulator
  • Integrated 33ohm series resistors on differential outputs, Zo=50Ω
  • Supports spread spectrum modulation, default is 0.5% down spread
  • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning
  • Selectable between one SRC differential push-pull pair and two single-ended outputs
  • Meets PCIEX Gen2 specification on dedicated SRC outputs. Muxed SRC outputs meet PCIEX Gen1 specification, except SRC1.
  • Meets PCIEX <85ps cycle-tocycle jitter for SRC[11:1]
  • Single-ended programmable slew rate control for RFI reduction

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Package Buy Sample
9ERS3165BGILF Active TSSOP 64 I Yes Tube Package Info
Availability
9ERS3165BGILFT Active TSSOP 64 I Yes Reel Package Info
Availability
9ERS3165BKILF Active VFQFPN 64 I Yes Tray Package Info
Availability
9ERS3165BKILFT Active VFQFPN 64 I 1 Reel Package Info
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ERS3165 Datasheet Datasheet PDF 518 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Other
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB