Additive jitter is defined as the added amount of jitter to the input signal caused by the device itself and can be calculated as:
Total Additive Jitter = sq root ((output clock jitter)² - (input clock rms jitter)²)
It assumes that the noise processes are random and the input noise is not correlated to the output noise. Additive jitter must be measured with a clock source where phase noise is below the noise floor of the buffer itself. Refer to application note AN-804 for more details. For questions not answered by the Knowledge Base, please submit a technical support request.


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Application Notes & White Papers
AN-804 IDT Clock Buffers Offer Low Additive Phase Jitter Application Note PDF 246 KB