Clock Jitter is commonly used to describe the performance requirements of oscillators and PLLs when driving high performance components like FPGAs, Microprocessors, and PHYs. It is important to use the jitter type that is most appropriate for the application of interest. Below are the three commonly used types of jitter:
Period Jitter – the time difference of the jittered clock period minus the nominal clock period. This is a time domain measurement, and can be expressed as RMS Period Jitter measured across 10K cycle. If expressed as P2P Period Jitter, then this must also be qualified with an assumed BER. This type of jitter is relevant for worst case timing analysis in Synchronous Interface and Synchronous Logic design.
High Frequency Jitter – typically quantified as C2C Jitter, which is the difference in the Period for successive cycles. This is a time domain measurement, and is measured across 1K cycles, and can be expressed as Peak value, and sometimes a P2P value. This type of jitter is relevant for Micro Complex, Motherboard Design, and Spread Spectrum generated clocks.
Frequency Domain Jitter – typically measured as Phase Noise and is a measure of the instantaneous phase deviations from the ideal; effectively a frequency domain quantification of clock jitter. Typically, this type of jitter is expressed as a PN Plot that shows the dBc values at the various carrier frequency offset points. This type of jitter is relevant for High Speed Serial communication and ADC use.
Refer to application note AN-827 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.


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Application Notes & White Papers
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB