The 5P35021 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The 5P35021 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5P35021 again through the I2C interface.
 
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pair of differential outputs that support LVCMOS, LVPECL, LVDS and LPHCSL. A Low Power 32.768kHz clock is supported with only less than 5μA current consumption for system RTC reference clock.
 

特長

  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance- Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 difference frequencies switch dynamically
  • Spread Spectrum clock support to lower system EMI
  • I2C interface
  • Also supports crystal input
  • Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version

製品選択

This device is factory-configurable. Try the Custom Part Configuration Utility.
発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Temp. Range Carrier Type 購入/サンプル
Active VFQFPN 20 I -40 to 85°C Tray
Availability
Active VFQFPN 20 I -40 to 85°C Reel
Availability
Active VFQFPN 20 2 -40 to 105°C Tray
Availability
Active VFQFPN 20 2 -40 to 105°C Reel
Availability

製品比較

5P35021 5L35021 5L35023 5P35023
Outputs (#) 5 5 7 7
Output Type LP-HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 3.3 1.8 1.8 3.3
Output Voltage (V) 1.8, 2.5, 3.3 1.8 1.8 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 3.0 x 3.0 x 1.0 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9 4.0 x 4.0 x 0.9

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
5P35021 Datasheet データシート PDF 673 KB
ユーザーガイド
Timing Commander Software for VersaClock 3S - 5P3502x マニュアル-ソフトウェア PDF 1.65 MB
VersaClock 3S - 5P3502x Family Programmer Board User Guide マニュアル PDF 1.27 MB
Timing Commander Installation Guide ガイド PDF 497 KB
アプリケーションノート、ホワイトペーパー
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) アプリケーションノート PDF 342 KB
AN-954 Layout and EMI Recommendations for Automotive Applications アプリケーションノート PDF 406 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products アプリケーションノート PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators アプリケーションノート PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs アプリケーションノート PDF 480 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-808 PCI Express/HCSL Termination アプリケーションノート PDF 137 KB
AN-806 Power Supply Noise Rejection アプリケーションノート PDF 438 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
製品変更通知 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
製品変更通知 PDF 5.61 MB
PCN# : TP1910-01 VBAT Power Domain Required 製品変更通知 PDF 110 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
Downloads
Timing Commander Installer (v1.16.2) ソフトウェア ZIP 18.44 MB
VersaClock 3S Timing Commander Personality File ソフトウェア ZIP 4.95 MB
5P35021 IBIS Model モデル-IBIS ZIP 74 KB
その他資料
PCI Express Timing Solutions Overview 概要 PDF 275 KB
5P35021 Reference Schematic 回路図 PDF 49 KB
VersaClock Family of Programmable Clocks Overview (Japanese) English 概要 PDF 1.31 MB
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技術概要 PDF 238 KB