The 5P35021 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The 5P35021 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5P35021 again through the I2C interface.
 
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pair of differential outputs that support LVCMOS, LVPECL, LVDS and LPHCSL. A Low Power 32.768kHz clock is supported with only less than 5μA current consumption for system RTC reference clock.
 

特性

  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance- Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 difference frequencies switch dynamically
  • Spread Spectrum clock support to lower system EMI
  • I2C interface
  • Also supports crystal input
  • Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version

产品选择

This device is factory-configurable. Try the Custom Part Configuration Utility.
下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Temp. Range Carrier Type Buy Sample
Active VFQFPN 20 I -40 to 85°C Tray
Availability
Active VFQFPN 20 I -40 to 85°C Reel
Availability
Active VFQFPN 20 2 -40 to 105°C Tray
Availability
Active VFQFPN 20 2 -40 to 105°C Reel
Availability

Product Comparison

5P35021 5L35021 5L35023 5P35023
Outputs (#) 5 5 7 7
Output Type LP-HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 3.3 1.8 1.8 3.3
Output Voltage (V) 1.8, 2.5, 3.3 1.8 1.8 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 3.0 x 3.0 x 1.0 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9 4.0 x 4.0 x 0.9

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
5P35021 Datasheet 数据手册 PDF 673 KB
使用指南与说明
Timing Commander Software for VersaClock 3S - 5P3502x 手册 - 软件 PDF 1.65 MB
VersaClock 3S - 5P3502x Family Programmer Board User Guide 手册 PDF 1.27 MB
Timing Commander Installation Guide 指南 PDF 497 KB
应用指南 &白皮书
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) 应用文档 PDF 342 KB
AN-954 Layout and EMI Recommendations for Automotive Applications 应用文档 PDF 406 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products 应用文档 PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.61 MB
PCN# : TP1910-01 VBAT Power Domain Required 产品变更通告 PDF 110 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
Downloads
Timing Commander Installer (v1.16.2) 软件 ZIP 18.44 MB
VersaClock 3S Timing Commander Personality File 软件 ZIP 4.95 MB
5P35021 IBIS Model 模型 - IBIS ZIP 74 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
5P35021 Reference Schematic 原理图 PDF 49 KB
VersaClock Family Overview 日本語 概览 PDF 785 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技术摘要 PDF 238 KB