The 5P49V6965 is a member of IDT's VersaClock® 6E programmable clock generator family. The 5P49V6965 is intended for high-performance consumer, networking, industrial, computing, and data-communications applications. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.
 
Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface.
 

特性

  • < 100mW core power (at 3.3V)
  • < 0.5ps RMS phase jitter (typical)
  • PCIe Gen 1/2/3/4/5 spread spectrum off
  • PCIe Gen 1/2/3/4 spread spectrum on
  • 1/10GbE, USB 3.0
  • Supports both crystal (8MHz–40MHz) and external clock input(1MHz–350MHz)
  • 4 universal outputs pairs: LVPECL, LVDS, HCSL, or 8 LVCMOS outputs
  • 4 independent frequencies with 0.001MHz–350MHz output range
  • Reference output
  • 1.8V / 2.5V / 3.3V core and output voltages
  • 2 programmable I²C addresses allowing multiple devices to be used in same system.
  • Up to 4 different configuration sets in OTP non-volatile memory
  • Supported by IDT Timing Commander™  software tool
  • Quick sampling and customization process supported by online-form submission
  • 4 x 4 mm 24-VFQFPN package
  • -40°C to +85°C operating temperature range

产品选择

This device is factory-configurable. Try the Custom Part Configuration Utility.
下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 24 I 是的 Tray
Availability
Active VFQFPN 24 I 是的 Reel
Availability

Product Comparison

5P49V6965 5P49V6967 5P49V6968 5P49V6975
Inputs (#) 2 2 2 1
Outputs (#) 5 9 11 5
Output Type HCSL, LVCMOS, LVDS, LVPECL HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL HCSL, LVCMOS, LVDS, LVPECL
Phase Jitter Typ RMS (ps) 0.500 0.500 0.500 0.500

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
5P49V6965 Datasheet 数据手册 PDF 784 KB
使用指南与说明
VersaClock 6E Family Register Descriptions and Programming Guide 手册 - 用户参考 PDF 872 KB
Timing Commander Installation Guide 指南 PDF 497 KB
应用指南 &白皮书
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter 应用文档 PDF 486 KB
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-970 Glitchless Frequency Adjustment using Fractional Output Divider 应用文档 PDF 717 KB
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) 应用文档 PDF 342 KB
AN-954 Layout and EMI Recommendations for Automotive Applications 应用文档 PDF 406 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products 应用文档 PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-905 Using VersaClock® 6 as Reference Clock for Xilinx® Series 7 FPGAs 应用文档 PDF 188 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.71 MB
PCN# : A2005-01(R1) Add UTL, Thailand and JCET, China as Alternate Assembly Locations 产品变更通告 PDF 725 KB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
Downloads
Timing Commander Installer (v1.16.3) 软件 ZIP 19.85 MB
VersaClock 6E Timing Commander Personality File v1.3.0 软件 ZIP 13.95 MB
5P49V6965 IBIS Model 模型 - IBIS ZIP 397 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
VersaClock Family Overview 日本語 概览 PDF 785 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Wired Broadband Applications Application Briefs PDF 686 KB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clocks for Xilinx Ultrascale FPGAs 技术摘要 PDF 256 KB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技术摘要 PDF 238 KB