The 5V49EE702 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE702 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of five 8-bit output dividers. Each output bank can be configured to support LVTTL, LVPECL, LVDS or HCSL logic levels. Out0 (Output 0) supports LVTTL standard only. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

特性

  • Four internal PLLs
  • Internal non-volatile EEPROM
  • Fast (400kHz) mode I2C serial interface
  • Input frequency range: 1 MHz to 200 MHz
  • Output frequency range: 4.9 kHz to 500 MHz
  • Reference crystal input with programmable linear load capacitance - Crystal frequency range: 8 MHz to 50 MHz
  • Three independently controlled VDDO (1.8V - 3.3V)
  • Each PLL has a 7-bit reference divider and a 12-bit feedback-divider
  • 8-bit output-divider blocks
  • Fractional division capability on one PLL
  • Two of the PLLs support spread spectrum generation capability
  • I/O Standards: - Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS - Outputs - LVPECL, LVDS and HCSL - Inputs - 3.3 V LVTTL/ LVCMOS
  • Programmable slew rate control
  • Programmable loop bandwidth
  • Programmable output inversion to reduce bimodal jitter
  • Redundant clock inputs with auto and manual switchover options
  • Individual output enable/disable
  • Power-down mode
  • 3.3V core VDD
  • Available in VFQFPN package
  • -40 to +85 C Industrial Temp operation

产品选择

下单器件 ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Not Recommended for New Designs 28 I 是的 Tube
Availability
Not Recommended for New Designs 28 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
5V49EE702 Datasheet 数据手册 PDF 477 KB
使用指南与说明
VersaClock3 Evaluation Board Setup Guide 手册 - 评估板 PDF 247 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.61 MB
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages 产品变更通告 PDF 36 KB
PCN# : A1310-01 Changed of Material Sets 产品变更通告 PDF 101 KB
PCN# : A1303-05 Stack Die Assembly with Interposer and Die Attach Material Change 产品变更通告 PDF 275 KB
PCN# : A1301-08 Stack Die Assembly with Interposer 产品变更通告 PDF 274 KB
Downloads
VersaClock 4.3 for Windows XP Service Pack 2&3 32-bit 软件 ZIP 118.00 MB
VersaClock 4.3 for Windows Vista Service Pack 2 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows Vista Service Pack 2 32-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 64-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows Vista RTM & Service Pack 1 32-bit 软件 ZIP 117.74 MB
VersaClock 4.3 for Windows 7 Professional 32-bit 软件 ZIP 118.54 MB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
VersaClock Family Overview 日本語 概览 PDF 785 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
VersaClock III Eval Board Schematics 原理图 PDF 80 KB
5V49EE702 Reference Schematic 其它 PDF 22 KB
VersaClock3-ProgrammableClocks 产品简述 PDF 1.61 MB
DesignTip-SpreadSpectrumClocking-VersaClock3 产品简述 PDF 199 KB