The 527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-02 aligns rising edges on PECLIN with FBIN at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the 527-04. For a CMOS input and PECL output with zero delay, use the 527-03.

Features

  • Packaged as 28-pin SSOP, Pb-free (150 mil body)
  • Synchronizes fractional clocks rising edges
  • PECL IN to CMOS OUT
  • Pin selectable dividers
  • Zero input to output skew
  • User determines the output frequency—no software needed
  • Slices frequency or period
  • Input clock frequency of 1.5 MHz to 200 MHz
  • Output clock frequencies from 4 MHz to 160 MHz
  • Very low jitter
  • Duty cycle of 45/55
  • Operating voltage of 3.3 V
  • Advanced, low-power CMOS process
  • Industrial temperature version available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
527R-02ILF Obsolete PCG28 QSOP 28 I Yes Tube
Availability
527R-02ILFT Obsolete PCG28 QSOP 28 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
527-02 Datasheet Datasheet PDF 217 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 245 KB
ICS527-01/-02 Demo Board Instructions Application Note PDF 89 KB
PCNs & PDNs
PDN# : U-12-03R4 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 72 KB
PDN# : U-12-03R3 Product Discontinuation Notice PDF 72 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB