2.5V LVDS,1:10 Glitchless Clock Buffer Terabuffer™ II

NOTICE - The following device(s) are recommended alternatives:

The 5T93GL10 2.5V differential clock buffer is a userselectable differential input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL10 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The 5T93GL10 outputs can be asynchronously enabled/ disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

Features

  • Guaranteed low skew: <25ps (maximum)Very low duty cycle distortion: <100ps (maximum)High speed propagation delay: <2ns (maximum)Up to 650MHz operationGlitchless input clock switchingSelectable inputsHot insertable and over-voltage tolerant inputs3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interfacesSelectable differential inputs to ten LVDS outputsPower-down modeAt power-up, FSEL should be LOW2.5V VDD-40°C to 85°C ambient operating temperatureAvailable in VFQFPN packageRecommends IDT5T9310 if glitchless input selection is not required

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5T93GL10NLGI Obsolete NLG40P1 VFQFPN 40 I Yes Tray Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-846 Termination - LVDS Application Note PDF 50 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-14-06R1 Revised Product Discontinuance Notice Product Discontinuation Notice PDF 407 KB Sep 7, 2014
PDN# : CQ-14-06 MANUFACTURING DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 192 KB Sep 3, 2014
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 13, 2012
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products Product Change Notice PDF 80 KB Dec 13, 2004
PCN#: L-0405-04 To comply with current EIA Std Product Change Notice PDF 143 KB May 17, 2004
PCN#: A-0310-01, Green Products Product Change Notice PDF 26 KB Oct 9, 2003
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016