2.5V Programmable Skew PLL Clock Driver

The 5T9950 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The 5T9950 has LVTTL outputs with 12mA balanced drive outputs.

Features

  • Ref input is 3.3V tolerant
  • 4 pairs of programmable skew outputs
  • Low skew: 185ps same pair, 250ps all outputs
  • Selectable positive or negative edge synchronization: Excellent for DSP applications
  • Synchronous output enable
  • Input frequency:– Std: 6MHz to 160MHz– A: 6MHz to 200MHz
  • Output frequency:– Std: 6MHz to 160MHz– A: 6MHz to 200MHz
  • 2x, 4x, 1/2, and 1/4 outputs
  • 3-level inputs for skew and PLL range control
  • PLL bypass for DC testing
  • External feedback, internal loop filter
  • 12mA balanced drive outputs
  • Low Jitter: <100ps cycle-to-cycle
  • Standard and A speed grades
  • Available in TQFP package
  • Not Recommended for New Design

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5T9950APFGI Obsolete PRG32 TQFP 32 I Yes Tray Availability
5T9950PFGI Obsolete PRG32 TQFP 32 I Yes Tray Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-14-01 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 539 KB Sep 2, 2014
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PDN# : CQ-14-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 538 KB Jan 25, 2014
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB Dec 21, 2013
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB Oct 26, 2013
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 20, 2012
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016