3.3V Programmable Skew Dual PLL Clock Driver TurboClock™ II

The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V995 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V995 has LVTTL outputs with 12mA balanced drive outputs.

Features

  • Ref input is 5V tolerant
  • 4 pairs of programmable skew outputs
  • Low skew: 185ps same pair, 250ps all outputs
  • Selectable positive or negative edge synchronization: Excellent for DSP applications
  • Synchronous output enable
  • Input frequency: 2MHz to 200MHz
  • Output frequency: 6MHz to 200MHz
  • 3-level inputs for skew and PLL range control
  • 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
  • PLL bypass for DC testing
  • External feedback, internal loop filter
  • 12mA balanced drive outputs
  • Low Jitter: <100ps cycle-to-cycle
  • Power-down mode
  • Lock indicator
  • Available in TQFP package
  • Not Recommended for New Design

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5V995PFGI Obsolete PPG44 TQFP 44 I Yes Tray Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB May 7, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB May 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 4, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 11, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 14, 2014
PCNs & PDNs
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB Dec 21, 2013
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB Oct 26, 2013