WAN PLL

The 82V3255 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only.

Features

  • Features 0.1 Hz to 560 Hz bandwidth
  • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
  • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
  • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
  • Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
  • Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
  • Integrates T0 DPLL and T4 DPLL
  • T4 DPLL locks independently or locks to T0 DPLL
  • Supports Forced or Automatic operating mode switch controlled by an internal state machine
  • the primary operating modes are Free- Run, Locked and Holdover
  • Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps)
  • Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
  • Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
  • Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
  • Supports programmable input-to-output phase offset adjustment
  • Limits the phase and frequency offset of the outputs
  • Supports manual and automatic selected input clock switch
  • Supports automatic hitless selected input clock switch on clock failure
  • Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
  • Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and a 2 kHz and an 8 kHz frame sync output signals
  • Provides 5 input clocks whose frequency cover from 2 kHz to 622.08 MHz
  • Provides 2 output clocks whose frequency cover from 1 Hz to 622.08 MHz
  • Provides output clocks for BITS, GPS, 3G, GSM, etc.
  • Supports PECL/LVDS and CMOS input/output technologies
  • Supports master clock calibration
  • Supports Line Card application
  • Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria
  • Serial microprocessor interface mode
  • IEEE 1149.1 JTAG Boundary Scan
  • Single 3.3 V operation with 5 V tolerant CMOS I/Os
  • 64-pin TQFP package, Green package options available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
82V3255EDG Active EDG64 TQFP 64 C Yes Tray
Availability
82V3255TFG Active PPG64 TQFP 64 C Yes Tray
Availability
82V3255TFG8 Active PPG64 TQFP 64 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
82V3255 Data Sheet Datasheet PDF 947 KB Jun 22, 2015
IDT82V3255 Data Sheet Change Notice Datasheet Change Notice PDF 86 KB Sep 28, 2005
Application Notes & White Papers
AN-850 82V3255 T0 DPLL State Transition Diagram Application Note PDF 57 KB May 14, 2014
PCNs & PDNs
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 567 KB Aug 25, 2016
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 13, 2016
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 14, 2016
PCN# : A1402-02 Alternate Assembly Locations Product Change Notice PDF 34 KB Sep 27, 2014
PCN# : A0902-04R1 DISCONTINUED OF 14MM X 14MM X 1.4MM TQFP-100 & 10MM X 10MM X 1.4MM TQFP-64 Product Change Notice PDF 1.81 MB Sep 21, 2009
PCN# : A0902-04 DISCONTINUED OF 14MM X 14MM X 1.4MM TQFP-100 & 10MM X 10MM X 1.4MM TQFP-64 Product Change Notice PDF 2.24 MB Mar 15, 2009
PCN# : A-0610-02 ASAT China as Alternate Facility for CABGA/CVBGA/FPBGA/TQFP/PQFP Product Change Notice PDF 252 KB Oct 18, 2006
A-0603-04 Transfer TQFP and PQFP from ASAT HK to ASAT China Product Change Notice PDF 164 KB May 9, 2006