The 853S6111I is a low skew 1-to-10 Differential Fanout Buffer, designed with clock distribution in mind, accepting two clock sources into an input MUX. The MUX is controlled by a CLK_SEL pin. This makes the 853S6111I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer. The device is designed on a SiGe process and can operate up to frequencies of 2.7GHz. This ensures negligible jitter introduction to the timing budget which makes it an ideal choice for distributing high frequency, high precision clocks across back planes and boards in communication systems. Internal temperature compensation guarantees consistent performance across various platforms.

Features

  • Ten differential LVPECL/ECL outputs
  • Two selectable differential input pairs
  • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, SSTL, CML
  • CLK, nCLK pair can accept the following differential input levels: HSTL, LVPECL, LVDS, SSTL, HCSL
  • Maximum input frequency: 2.7GHz
  • Output skew: 35ps (maximum)
  • Part-to-part skew: 250ps (maximum), fo > 1.5GHz
  • Additive phase jitter, RMS: 0.123ps (typical)
  • LVPECL and HSTL mode operating voltage supply range: VCC = 2.5V±5% or 3.3V±5%, VEE = 0V
  • ECL mode operating voltage supply range: VEE = -3.3V±5% or -2.5V±5%, VCC = 0V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
853S6111AYILF Obsolete DXG32 PTQFP 32 I Yes Tray
Availability
853S6111AYILFT Obsolete DXG32 PTQFP 32 I Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCNs & PDNs
PDN# : N-13-03R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 72 KB
PDN# : N-13-03 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 69 KB
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB