Low Skew, 1-to-6 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer

The 87931I-147 is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer. With output frequencies up to 240MHz, the 87931I is targeted for high performance clock applications. Along with a fully integrated PLL, the 87931I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay". Selectable clock inputs, CLK1 and differential CLK0, nCLK0 support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A, B and C are controlled by the DIV_SELA, DIV_SELB and DIV_SELC, respectively. For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When LOW, the nMR input resets the internal dividers and forces the outputs to the high impedance state. The effective fanout of the 87931I-147 can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines.

Features

  • Fully integrated PLL
  • Six LVCMOS/LVTTL outputs, 7? typical output impedance
  • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications
  • Maximum output frequency: 240MHz
  • VCO range: 220MHz to 480MHz
  • External feedback for "zero delay" clock regeneration
  • Output skew: 165ps (maximum)
  • Cycle-to-cycle jitter: 45ps (maximum)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Contact IDT for replacement device at clocks@idt.com

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
87931AYI-147LF Obsolete PRG32 TQFP 32 I Yes Tray Availability
87931AYI-147LFT Obsolete PRG32 TQFP 32 I Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS87931I-147 DATASHEET Datasheet PDF 381 KB Aug 15, 2013
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PDN# : CQ-13-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 302 KB Jul 24, 2013
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB Jun 13, 2013
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB Mar 30, 2013
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB Feb 27, 2013
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
87931I-147 IBIS Model Model - IBIS ZIP 44 KB Nov 3, 2009