DDR Zero Delay Clock Buffer

DDR Zero Delay Clock Buffer

Features

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 266MHz (DDR 533)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
93732AFLF Obsolete PYG28 SSOP 28 C Yes Tube Availability
93732AFLFT Obsolete PYG28 SSOP 28 C Yes Reel Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
ics93732 Datasheet PDF 100 KB Jun 19, 2008
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1305-01 Gold Wire to Copper Wire Product Change Notice PDF 148 KB Jul 28, 2013
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 23, 2013
PDN# : K-08-09 PRODUCT DISCONTINUANCE NOTICE Product Delete Notice PDF 47 KB Jul 19, 2008
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016