2 DIMM DDR Fanout Buffer


  • Recommended Application: DDR fan out buffer for VIA P4x266/400 & PT800/880 chipsets Max. frequency supported: 266 MHz (DDR533)
  • Low skew, fanout buffer
  • 1 to 6 differential clock distribution
  • I2C for functional and output control
  • Feedback pin for input to output synchronization
  • Supports up to 2 DDR DIMMs
  • CMOS level control signal input

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
93789DFLF Obsolete PYG28 SSOP 28 C Yes Tube
93789DFLFT Obsolete PYG28 SSOP 28 C Yes Reel

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 23, 2013
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016
PC Clocks Contact Info Misc PDF 62 KB May 28, 2007