DDR II fanout buffer for VIA Chipset

Features

  • Low skew, fanout buffer
  • I2C for functional and output control
  • Single bank 1-6 differential clock distribution
  • 1 pair of differential feedback pins for input to output
  • synchronizationSupports up to 2 DDR DIMMs
  • 400MHz (DDRII 800) output frequency support
  • Programmable skew through SMBus
  • Frequency defect control thorugh SMBus
  • Individual output control programmable through SMBus

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9P956AFLF Obsolete PYG28 SSOP 28 C Yes Tube
Availability
9P956AFLFT Obsolete PYG28 SSOP 28 C Yes Reel
Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCNs & PDNs
PDN# : K-13-01R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 125 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
PDN# : K-13-01R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 125 KB
PDN# : K-13-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 122 KB
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
PC Clocks Contact Info Misc PDF 62 KB