1-to-12 Differential Clock Buffer

The CV128 differential buffer complies with Intel DB1200G rev. 0.5, and is designed to work in conjunction with the main clock of CK409, CK410/CK410M and CK410B etc., PLL is off in bypass mode and no clock detect.

Features

  • Compliant with Intel DB1200G rev. 0.5
  • DIF Clock Support ? 12differential clock output pairs @ 0.7 V ? 50 ps skew performance (same gear)
  • OE pin Control of All Outputs
  • 3.3 V Operation
  • Gear Ratio supporting generation of clocks at a different frequency ratioed from the input.
  • Split outputs supporting options of 2 outputs @1:1 and remaining 10 pairs at an alternate gear
  • Pin level OE control of individual outputs
  • Multiple output frequency options up to 400Mhz as a gear ratio of input clocks of 100-400Mhz
  • Output is HCSL compatible
  • SMBus Programmable configurations
  • PLL Bypass Configurable
  • SMBus address configurable to allow multiple buffer control in a single control network
  • Programmable Bandwidth
  • Glitchfree transition between frequency states
  • Available in SSOP and TSSOP packages

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
CV128PAG Obsolete PAG56 TSSOP 56 C Yes Tube Availability
CV128PVG Obsolete PVG56 SSOP 56 C Yes Tube Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
CV128 Datasheet Datasheet PDF 79 KB Jul 1, 2007
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-831 The Crystal Load curve Application Note PDF 308 KB Sep 22, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB May 7, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB May 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB May 4, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 11, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 14, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 20, 2012