The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/ PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6210 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.


  • Dual 1:5 differential clock distribution
  • 30 ps maximum device skew
  • Fully differential architecture from input to all outputs
  • SiGe technology supports near-zero output skew
  • Supports DC to 3GHz operation of clock or data signals
  • ECL/PECL compatible differential clock outputs
  • ECL/PECL compatible differential clock inputs
  • Single 3.3V, –3.3V, 2.5V or –2.5V supply
  • Standard 32 lead LQFP and VFQFN packages
  • Industrial temperature range
  • Pin and function compatible to the MC100EP210
  • 32-lead Pb-free Package Available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MC100ES6210AC Obsolete PRG32 TQFP 32 C Yes Tray
MC100ES6210ACR2 Obsolete PRG32 TQFP 32 C Yes Reel

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
MC100ES6210 Datasheet Datasheet PDF 310 KB Feb 20, 2013
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB Feb 15, 2014
PDN# : N-12-48R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 138 KB Jun 13, 2013
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB Jun 13, 2013
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB Mar 30, 2013
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB Feb 27, 2013
PDN# : N-12-48R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB Feb 2, 2013
PDN# : N-12-48 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB Dec 20, 2012
PCN# : A-0610-02 ASAT China as Alternate Facility for CABGA/CVBGA/FPBGA/TQFP/PQFP Product Change Notice PDF 252 KB Oct 18, 2006
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
MC100ES6210 2.5V IBIS Model Model - IBIS ZIP 7 KB Jan 28, 2010