Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.

Features

  • 1:20 differential clock fanout buffer
  • 100 ps maximum device skew
  • SiGe technology
  • Supports DC to 2 GHz operation of clock or data signals
  • ECL/PECL compatible differential clock outputs
  • ECL/PECL/HSTL compatible differential clock inputs
  • Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply
  • Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics
  • Supports industrial temperature range
  • Pin and function compatible to the MC100EP221
  • 52-lead Pb-free Package Available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MC100ES6221AE Obsolete EPG52 PTQFP 52 C Yes Tray Availability

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
MC100ES6221 Datasheet Datasheet PDF 401 KB Oct 14, 2013
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCNs & PDNs
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB Oct 14, 2014
PDN# : N-12-36R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 93 KB Jun 13, 2013
PDN# : N-12-36R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 69 KB Dec 17, 2012
Other
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 24, 2016

Software & Tools

Title Other Languages Type Format File Size Date
MC100ES6221 2.5V IBIS Model Model - IBIS ZIP 8 KB Jan 28, 2010