NOTICE - The following device(s) are recommended alternatives:
The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The ES6535 is ideal for high performance clock distribution applications.


  • 4 differential LVPECL outputs
  • 2 selectable LVCMOS/LVTTL inputs
  • 1 GHz maximum output frequency
  • Translates LVCMOS/LVTTL levels to LVPECL levels
  • 30 ps maximum output skew
  • 190 ps part-to-part skew
  • 3.3 V operating range
  • 20-lead TSSOP package
  • Ambient temperature range –40°C to +85°C
  • 20-lead Pb-free package available

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
MC100ES6535EJ Obsolete PGG20 TSSOP 20 C Yes Tube
MC100ES6535EJR2 Obsolete PGG20 TSSOP 20 C Yes Reel

Technical Documentation

Title Other Languages Type Format File Size Date
Datasheets & Errata
MC100ES6535 Datasheet Datasheet PDF 253 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PDN# : N-12-23R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 71 KB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB